The present invention relates to systems and methods for AC testing of a target circuit.
In general, testing a target circuit, such as an integrated circuit (IC), prior to packaging may reveal problems associated with the individual ICs and also with the IC fabrication process preceding the packaging step. Testing an IC after packaging may reveal problems arising from the packaging process steps, such as die attachment, wire bonding, among other steps.
So called scan chain testing techniques may be employed for testing IC circuits before and/or after packaging. Existing scan chain test operations for DC testing include scanning a known sequence of bits into a series of respective latches (flip flops) within the IC circuit. The latches are selected to direct the scanned bits to the input(s) of the target circuit, such as combinational logic, Static Random Access Memory (SRAM), etc. The target circuit is provided with a significant amount of time to let the input sequence of bits settle at the input(s) and outputs of the gates, memory cells, etc., such that test output bits are produced in response to the input bits. In other words, no dynamic testing is conducted. The output bits are directed to a selected series of output latches of the IC. Commands are then issued to scan the test output bits from the output latches, and the output bits are compared to a known template to determine whether the target circuit is operational.
Notably, the input latches and output latches are typically already part of the IC and, under normal operating modes, perform functions that permit the IC to operate. The testing designer, however, selects the input and output latches from among the latches of the IC to be used in the scan chain testing process. Selector circuits may be employed to switch the input/output connections of the selected latches between normal operating modes and the scan chain testing mode. Since the DC scan chain testing process does not perform dynamic (AC) testing, virtually any of the existing latches of the IC may be selected as input/output latches for the scan chain test process no matter where (how far) they may be located relative to the inputs/output of the target circuit, the impedances of the interconnections, or potential sources of electromagnetic interference.
Existing systems for AC testing may also involve selecting input and output latches from among existing latches of the IC to be used in an AC testing process. However, since a dynamic test is desired, the input bits to the target circuit must be rapidly provided in order to exercise the target circuit in ways that may uncover defects, such as input/output set up times, propagation delays, impedance characteristics, electromagnetic interference sources, etc. Thus, AC testing techniques typically use a CPU (Central Processing Unit) external to the target circuit to drive data into and out of selected input/output latches adjacent to the target circuit. Generally, the CPU is coupled to respective input and output connections for a portion of a circuit being tested which are generally within a limited, localized region of the test circuit. However, it is cumbersome and complex to connect an external CPU in this manner to all portions of a circuit for which testing is sought.
A special case of circuit testing is that of Array Built In Self Test (ABIST). An ABIST circuit can include an ABIST engine, an array macro, which in turn includes a memory array, and communication links between the ABIST engine and the array macro.
Herein, an array macro generally corresponds to a circuit that includes a memory array which may also be referred to as a “memory core” and additional functionality to enable communication between the memory core and devices external to the array macro.
For DC testing, the ABIST engine generates “write data” (for storage in the array) and address values and sends both to scannable latches in the array macro. Thereafter, the storage data are stored in the specified addresses in a memory array within the array macro. The ABIST engine then issues a read instruction to the array macro, retrieves output data from the array macro, and compares the retrieved data to expectation data generated by the ABIST engine. The functionality of the array macro is then determined by comparing the expectation data (which generally corresponds to the original write data) with the data retrieved from the array macro.
While the above process is effective for DC testing an array macro, the speed at which data can be provided to the memory array is limited by the rate at which the write data and address values can be transmitted from the ABIST engine to the scannable latches of the array macro. A few cycles of continuous data transmission to the memory array may be obtained by using multiple sets of (such as two or three) input latches for inputting data to a single set of memory array input lines. However, it is cumbersome to add hardware to the array macro in this manner. Moreover, sending only two or three sets of input “write data” in rapid succession, for AC testing purposes, does not sufficiently exercise the various features of the array macro for circuit evaluation purposes.
A similar problem exists with regard to reading data from the target circuit, and comparing the read data to a known template for evaluation purposes. Specifically, the deployment of a serial communication link to direct read data out of an array macro to an ABIST engine may serve as a data traffic bottleneck for the process of extracting data from the target circuit. Slowing down the data transfer out of a memory array to accommodate the data communication bandwidth of this serial link would remove the ability to test the dynamic characteristics of the memory array during high frequency operation, which is representative of the circuit under normal operating conditions.
Accordingly, it would be desirable to be able to write data to a target circuit, read data from the target circuit, and compare the read data to a known template rapidly enough to enable testing the dynamic characteristics of the circuit under test.